The present invention relates to semiconductor devices and methods for fabricating the same, and more particularly relates to improving reliability of the semiconductor devices.
Recently, as semiconductor devices have been downsized, spacing between gate electrodes has been reduced. However, it is extremely difficult to reduce the thickness of the gate electrodes because this reduction increases the resistance and also prolongs the delay time. Accordingly, the reduction in thickness of the gate electrodes has not advanced. As a result, the aspect ratio of the gate electrodes (which is herein the ratio of the height of the gate electrodes to the spacing between the gate electrodes) increases so that it is difficult to bury an interlevel dielectric film in the gap between the gate electrodes by a known method.
If a void is present in part of the interlevel dielectric film through which a contact hole is to be formed and which is located between the gate electrodes, there arises a problem that deposition components created by dry etching are attached to the bottom of the contact hole to cause a contact failure.
As a method for solving this problem, a sacrificial sidewall process was proposed (in the 61st Japan Society of Applied Physics, Annual Meeting No.2, p. 781 [5p-ZE-3]). In this process, a sidewall is removed after source and drain are defined so that the spacing between gate electrodes becomes wider and then an interlevel dielectric film is buried in a gap between the gate electrodes.
The sacrificial sidewall process will be hereinafter described with reference to FIGS. 10A through 11B.
First, in a process step shown in FIG. 10A, isolation regions 2 each made of a trench isolation are formed in a semiconductor substrate 1, and then gate electrodes 6 are formed on the substrate. Each of the gate electrodes 6 includes: a gate insulating film 3 of a silicon oxynitride film; a lower gate electrode 4a of polysilicon; an upper gate electrode 4b of a multilayer metal film; and a gate protective layer 5 of a silicon nitride film, in that order from below. Thereafter, impurity ions are implanted into the semiconductor substrate 1 using the gate electrodes 6 as a mask, thereby defining first doped regions 7 to be LDD regions or extension doped regions.
Next, in a process step shown in FIG. 10B, an underlying insulating film 8 of an NSG film (a silicon oxide film containing no impurities), a protective insulating film 9 of a silicon nitride film, and a sidewall insulating film 10 of a BPSG film are formed in this order over the substrate. In this case, the sidewall insulating film 10 is formed by an atmospheric or a subatmospheric CVD process so as to have a sufficient etch selectivity with respect to the underlying insulating film 8 and the protective insulating film 9 during a subsequent wet etching process.
Then, in a process step shown in FIG. 11A, the sidewall insulating film 10, the protective insulating film 9 and the underlying insulating film 8 are etched in this order by anisotropic dry etching, thereby forming sidewalls 11 each having a multilayer structure including an underlying insulating film 8a, a protective insulating film 9a and a sidewall insulating film 10a. Subsequently, impurity ions are implanted into the semiconductor substrate 1 using the gate electrodes 6, the sidewalls 11 and the isolation regions 2 as a mask, thereby defining second doped regions 12 to be heavily-doped source/drain regions.
Thereafter, in a process step shown in FIG. 11B, the sidewall insulating film 10a made of a BPSG film and included in the sidewalls 11 is selectively removed by wet etching, thereby forming L-shaped sidewalls 11a including the underlying insulating film 8a and the protective insulating film 9a so that the spacing between the L-shaped sidewalls 11a formed on side faces of the gate electrodes 6 is sufficiently wide. Subsequently, an interlevel dielectric film 13 of a BPSG film is deposited by a CVD process over the substrate so as to fill in the gap between the L-shaped sidewalls 11a. Then, the surface of the interlevel dielectric film 13 is planarized by a CMP process.